In the field of high density non-volatile data storage the floating gate technology based NAND array architecture is an important factor, in particular due to the simplicity of the production process, low costs per bit, especially when implementing multilevel storage techniques, and good scalability of the process for devices having a minimal feature size F above 50 nm. However, for devices having a minimal feature size F below 50 nm, significant difficulties regarding the production process are expected due to increasing interaction between the floating gates of adjacent memory cells, degraded controllability of the gate of the floating gate transistor, punch-through during reading and programming as well as low read currents. An alternative to the floating gate technology is the NROM technology, which provides a capacity for digital data storage of two bits/cell and the 3F2/bit virtual ground architecture. However, the scalability below a minimal feature size F of 50 nm of this technique is questionable due to the presence of high electrical fields between source and drain during operation. An expansion of the digital data storage capacity for two bits/cell to four bits/cell by providing four different states at each of the pn-junctions is difficult due to the “second bit effect,” that refers to a cross talk of the second bit. Furthermore, the scalability of the NROM-transistor is delimited when the ONO trapping layer has a large effective oxide thickness (EOT).
What is desired is a memory, a process for the fabrication of such a memory and a for operating such a memory, wherein the memory has the functionality of an NROM wherein the dimensions of a memory cell of the memory can be scaled down to a minimum feature size F below 50 nm.